Settings for registers of ADC 28 Click driver. More...
Detailed Description
Settings for registers of ADC 28 Click driver.
Macro Definition Documentation
◆ ADC28_4_LSB_MASK
| #define ADC28_4_LSB_MASK 0x000F |
◆ ADC28_ADC_RESOLUTION
| #define ADC28_ADC_RESOLUTION 4096.0f |
ADC 28 data resolution and VDD setting.
Specified setting for data resolution and VDD of ADC 28 Click driver.
◆ ADC28_AUTO_SEQ_ALL_CH
| #define ADC28_AUTO_SEQ_ALL_CH 0xFF |
◆ ADC28_AUTO_SEQ_CH0
| #define ADC28_AUTO_SEQ_CH0 0x01 |
ADC 28 AUTO_SEQ_CH_SEL bitmask setting.
Specified setting for AUTO_SEQ_CH_SEL bitmask of ADC 28 Click driver.
◆ ADC28_AUTO_SEQ_CH1
| #define ADC28_AUTO_SEQ_CH1 0x02 |
◆ ADC28_AUTO_SEQ_CH2
| #define ADC28_AUTO_SEQ_CH2 0x04 |
◆ ADC28_AUTO_SEQ_CH3
| #define ADC28_AUTO_SEQ_CH3 0x08 |
◆ ADC28_AUTO_SEQ_CH4
| #define ADC28_AUTO_SEQ_CH4 0x10 |
◆ ADC28_AUTO_SEQ_CH5
| #define ADC28_AUTO_SEQ_CH5 0x20 |
◆ ADC28_AUTO_SEQ_CH6
| #define ADC28_AUTO_SEQ_CH6 0x40 |
◆ ADC28_AUTO_SEQ_CH7
| #define ADC28_AUTO_SEQ_CH7 0x80 |
◆ ADC28_BUSY_CFG_BUSYTIME_1_2US
| #define ADC28_BUSY_CFG_BUSYTIME_1_2US 0x00 |
ADC 28 BUSY_CFG register setting.
Specified setting for BUSY_CFG register of ADC 28 Click driver.
◆ ADC28_BUSY_CFG_BUSYTIME_6_0US
| #define ADC28_BUSY_CFG_BUSYTIME_6_0US 0xC0 |
◆ ADC28_CHANNEL_0
| #define ADC28_CHANNEL_0 0x00 |
ADC 28 channel selection setting.
Specified setting for channel selection of ADC 28 Click driver.
◆ ADC28_CHANNEL_1
| #define ADC28_CHANNEL_1 0x01 |
◆ ADC28_CHANNEL_2
| #define ADC28_CHANNEL_2 0x02 |
◆ ADC28_CHANNEL_3
| #define ADC28_CHANNEL_3 0x03 |
◆ ADC28_CHANNEL_4
| #define ADC28_CHANNEL_4 0x04 |
◆ ADC28_CHANNEL_5
| #define ADC28_CHANNEL_5 0x05 |
◆ ADC28_CHANNEL_6
| #define ADC28_CHANNEL_6 0x06 |
◆ ADC28_CHANNEL_7
| #define ADC28_CHANNEL_7 0x07 |
◆ ADC28_CHANNEL_MASK
| #define ADC28_CHANNEL_MASK 0x0F |
◆ ADC28_DATA_CFG_APPEND_STATUS_ALERT
| #define ADC28_DATA_CFG_APPEND_STATUS_ALERT 0x20 |
◆ ADC28_DATA_CFG_APPEND_STATUS_CHID
| #define ADC28_DATA_CFG_APPEND_STATUS_CHID 0x10 |
◆ ADC28_DATA_CFG_APPEND_STATUS_NONE
| #define ADC28_DATA_CFG_APPEND_STATUS_NONE 0x00 |
ADC 28 DATA_CFG register setting.
Specified setting for DATA_CFG register of ADC 28 Click driver.
◆ ADC28_DATA_CFG_FIX_PAT
| #define ADC28_DATA_CFG_FIX_PAT 0x80 |
◆ ADC28_DEVICE_ADDR_R1_0_R2_OPEN
| #define ADC28_DEVICE_ADDR_R1_0_R2_OPEN 0x17 |
ADC 28 device address setting.
Specified setting for device slave address selection of ADC 28 Click driver.
◆ ADC28_DEVICE_ADDR_R1_100K_R2_OPEN
| #define ADC28_DEVICE_ADDR_R1_100K_R2_OPEN 0x14 |
◆ ADC28_DEVICE_ADDR_R1_OPEN_R2_0
| #define ADC28_DEVICE_ADDR_R1_OPEN_R2_0 0x10 |
◆ ADC28_DEVICE_ADDR_R1_OPEN_R2_100K
| #define ADC28_DEVICE_ADDR_R1_OPEN_R2_100K 0x13 |
◆ ADC28_DEVICE_ADDRESS
| #define ADC28_DEVICE_ADDRESS ADC28_DEVICE_ADDR_R1_0_R2_OPEN |
◆ ADC28_EVENT_COUNT_LIMIT
| #define ADC28_EVENT_COUNT_LIMIT 0x0F |
◆ ADC28_EVENT_COUNT_MASK
| #define ADC28_EVENT_COUNT_MASK 0x0F |
◆ ADC28_GENERAL_CFG_DWC_EN
| #define ADC28_GENERAL_CFG_DWC_EN 0x10 |
◆ ADC28_GENERAL_CFG_RST
| #define ADC28_GENERAL_CFG_RST 0x01 |
ADC 28 GENERAL_CFG register setting.
Specified setting for GENERAL_CFG register of ADC 28 Click driver.
◆ ADC28_GENERAL_CFG_STATS_EN
| #define ADC28_GENERAL_CFG_STATS_EN 0x20 |
◆ ADC28_HIGH_THR_LSB_MASK
| #define ADC28_HIGH_THR_LSB_MASK 0xF0 |
◆ ADC28_HIGH_THR_MSB_MASK
| #define ADC28_HIGH_THR_MSB_MASK 0xFF |
◆ ADC28_HYSTERESIS_LIMIT
| #define ADC28_HYSTERESIS_LIMIT 0x0F |
◆ ADC28_HYSTERESIS_MASK
| #define ADC28_HYSTERESIS_MASK 0x0F |
◆ ADC28_LOW_THR_LSB_MASK
| #define ADC28_LOW_THR_LSB_MASK 0xF0 |
◆ ADC28_LOW_THR_MSB_MASK
| #define ADC28_LOW_THR_MSB_MASK 0xFF |
◆ ADC28_OPCODE_BLOCK_READ
| #define ADC28_OPCODE_BLOCK_READ 0x30 |
◆ ADC28_OPCODE_BLOCK_WRITE
| #define ADC28_OPCODE_BLOCK_WRITE 0x28 |
◆ ADC28_OPCODE_CLEAR_BIT
| #define ADC28_OPCODE_CLEAR_BIT 0x20 |
◆ ADC28_OPCODE_SET_BIT
| #define ADC28_OPCODE_SET_BIT 0x18 |
◆ ADC28_OPCODE_SINGLE_READ
| #define ADC28_OPCODE_SINGLE_READ 0x10 |
ADC 28 I2C OPCODE commands setting.
Specified setting for I2C OPCODE commands of ADC 28 Click driver.
◆ ADC28_OPCODE_SINGLE_WRITE
| #define ADC28_OPCODE_SINGLE_WRITE 0x08 |
◆ ADC28_OPMODE_CFG_CLK_DIV_0_75MS
| #define ADC28_OPMODE_CFG_CLK_DIV_0_75MS 0x00 |
ADC 28 OPMODE_CFG register setting.
Specified setting for OPMODE_CFG register of ADC 28 Click driver.
◆ ADC28_OPMODE_CFG_CLK_DIV_1_5MS
| #define ADC28_OPMODE_CFG_CLK_DIV_1_5MS 0x01 |
◆ ADC28_OPMODE_CFG_CLK_DIV_3MS
| #define ADC28_OPMODE_CFG_CLK_DIV_3MS 0x02 |
◆ ADC28_OPMODE_CFG_CLK_DIV_6MS
| #define ADC28_OPMODE_CFG_CLK_DIV_6MS 0x03 |
◆ ADC28_OPMODE_CFG_CONV_MODE_AUTO
| #define ADC28_OPMODE_CFG_CONV_MODE_AUTO 0x20 |
◆ ADC28_OPMODE_CFG_CONV_MODE_MANUAL
| #define ADC28_OPMODE_CFG_CONV_MODE_MANUAL 0x00 |
◆ ADC28_SEQUENCE_CFG_SEQ_MODE_AUTO
| #define ADC28_SEQUENCE_CFG_SEQ_MODE_AUTO 0x01 |
◆ ADC28_SEQUENCE_CFG_SEQ_MODE_MANUAL
| #define ADC28_SEQUENCE_CFG_SEQ_MODE_MANUAL 0x00 |
ADC 28 SEQUENCE_CFG register setting.
Specified setting for SEQUENCE_CFG register of ADC 28 Click driver.
◆ ADC28_SEQUENCE_CFG_SEQ_START
| #define ADC28_SEQUENCE_CFG_SEQ_START 0x10 |
◆ ADC28_SYSTEM_STATUS_BOR
| #define ADC28_SYSTEM_STATUS_BOR 0x01 |
ADC 28 SYSTEM_STATUS register setting.
Specified setting for SYSTEM_STATUS register of ADC 28 Click driver.
◆ ADC28_SYSTEM_STATUS_I2C_SPEED
| #define ADC28_SYSTEM_STATUS_I2C_SPEED 0x20 |
◆ ADC28_SYSTEM_STATUS_SEQ_STATUS
| #define ADC28_SYSTEM_STATUS_SEQ_STATUS 0x40 |
◆ ADC28_THRESHOLD_LIMIT
| #define ADC28_THRESHOLD_LIMIT 0x0FFF |
ADC 28 data threshold, hysteresis and even count setting.
Specified setting for threshold, hysteresis and event count of ADC 28 Click driver.
◆ ADC28_VDD_3V3
| #define ADC28_VDD_3V3 3.3f |
◆ ADC28_VDD_5V
| #define ADC28_VDD_5V 5.0f |
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